1. Field of the Invention
The present invention relates to a chip-size package (CSP) semiconductor, and more particularly to an improved chip-size package semiconductor employing a single layer substrate specially designed to receive a conventional LOC (lead on chip) type chip as it is, thus further downsizing its thickness and improving productivity.
2. Description of Related Art
In order to downsize the semiconductor package, the CSP semiconductor have been generally proposed. The CSP semiconductor, when it is completed, has its size smaller than a conventional chip size and has been developed in various way for the purpose of reducing its thickness and downsizing its size.
Hereinafter, two typical CSP semiconductors in the prior art will be briefly described.
FIG. 1 shows a conventional CSP semiconductor receiving a LOC type chip. The CSP semiconductor comprises LOC type chip 1; and a lead frame 2 attached to the lower surface of the chip through an adhesive means 4 and supporting the chip thereon. The chip 1 and the lead frame 2 are wire bonded and interconnected, and the assembly of the chip 1 and the read frame 2 are molded by a molding compound.
However, since the CSP semiconductor employs a conventional lead frame formed in a certain shape beforehand, it decreases the efficiency of work. That is, in molding, there is a fear that the molding compound is not completely filled between the chip and the lead frame, and thus forming undesirable cavities and the lead frame is deformed. In trimming, chipping and cracking of the package may occur near the lead frame, and it is difficult to adjust the thickness of the package.
Therefore, in order to solve the above problem, the CSP structure employing a co-fired ceramic substrate, not using the lead frame, has been proposed. That is, the CSP structure has the a substrate having its both surface formed a signal circuit pattern, formed with a plurality of via for transmitting the signal between both side thereof. The chip is mounted on the substrate, and formed with bumpers for electrically interconnecting the chip and the substrate at the bottom of the chip. And then the whole body of the structure is under-filled, thereby to complete the package.
However, since it is not easy to form the via in the precise position on the substrate, the production cost of the package increases and mass production is restricted. Another problem with the prior art is that the reduction of the package's thickness is limited since the bumpers are meddled between the chip and the substrate.